Reduction of the size and the inherent features of semiconductor devices (e.g., Metal-Oxide Semiconductor (MOS) devices) has enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the MOS devices and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and drain of a MOS device alters a resistance associated with the channel region, thereby affecting a performance of the MOS device. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the MOS device, which, assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the MOS device.
To further enhance the performance of MOS devices, stress may be introduced in the channel region of a MOS device to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (“NMOS”) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type MOS (“PMOS”) device in a source-to-drain direction.
A commonly used method for applying compressive stress to the channel regions of PMOS devices is growing SiGe stressors in the source and drain regions. Such a method typically includes the steps of forming a gate stack on a semiconductor substrate, forming spacers on sidewalls of the gate stack, forming recesses in the silicon substrate along gate spacers, epitaxially growing SiGe stressors in the recesses and annealing. Since SiGe has a greater lattice constant than silicon, it expands after annealing and applies a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor.
The above-discussed method, however, suffers from the drawback of pattern-loading effects, which occur due to a difference in pattern densities. The pattern-loading effects pertain to a phenomenon occurring upon simultaneous epitaxial growth in a region of a higher pattern density and a region of a lower pattern density. Due to a difference in growth rates of a film from one location to another, the amount of growth becomes locally dense or sparse depending on the local pattern density, and this causes non-uniformity in the thicknesses of the resulting film. Large variations in effective pattern density have been shown to result in significant and undesirable film thickness variation. For example, active regions that are surrounded by regions having a large area ratio of dielectrics (meaning less surface area for the epitaxial growth) would have faster growth of the epitaxy layer than other active regions. In addition, the composition of the epitaxy layer at the loosely packed active regions is also different from that of densely packed active regions. Particularly, this non-uniformity makes device formation process hard to control and device performance may be adversely affected.
The pattern-loading effects can be reduced by adjusting epitaxy parameters, such as reducing the process pressure or adjusting precursor flow rates. However, as a side effect, other epitaxy properties, such as composition, are also impacted by the changes of the pressure and the gas flow rate. Additionally, the amount of reduction in the pattern-loading effects using this method is not satisfactory.